Voltage sustaining layer with opposite-doped islands for semiconductor power devices

ABSTRACT

A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 11/365,223, now, U.S. Pat. No. 7,271,067 filed Mar. 1, 2006 which is a divisional application of U.S. patent application Ser. No. 10/860,435, filed Jun. 3, 2004, now U.S. Pat. No. 7,227,197; which is a divisional application of U.S. patent application Ser. No. 10/382,027, Mar. 5, 2003, now U.S. Pat. No. 6,936,867; which is a divisional application of U.S. patent application Ser. No. 08/953,077, filed Oct. 17, 1997, now U.S. Pat. No. 6,635,906; which is a continuation of U.S. patent application Ser. No. 08/598,386, filed Feb. 8, 1996, now abandoned; which is a continuation of U.S. patent application Ser. No. 08/268,339, filed Jun. 30, 1994, now abandoned.

BACKGROUND OF THE INVENTION

This invention relates to semiconductor high voltage devices, and specifically to semiconductor high voltage devices with voltage sustaining layer containing floating regions.

It is well-known that in many semiconductor devices, such as VD-MOST and SIT, a high sustaining voltage always accompanies a high specific on-resistance. This is due to the fact that, for a high sustaining voltage, thickness of a voltage sustaining layer should be large and doping concentration of the voltage sustaining layer should be low, so as the peak field does not exceed the critical field for breakdown -E_(C), which is normally expressed by E_(C)=8.2×10⁵×V_(B) ^(−0.2) V/cm for silicon, where V_(B) is the breakdown voltage of the voltage sustaining layer.

In a uniformly doped n-type voltage sustaining layer between p+-region and n+-region, in order to obtain a minimum specific on-resistance at a given breakdown voltage, a doping concentration N_(D) and a thickness W of the voltage sustaining layer are optimized such that a maximum field is at p+-n-junction and its value is equal to E_(C), a minimum field is at n+-n-junction and equal to E_(C)/3. For silicon device, N _(D)=1.9×10¹⁸ ×V _(B) ^(−1.4) cm ⁻³   (1) W=1.8×10⁻² ×V _(B) ^(−1.2) μm ⁻²   (2) (see, e.g., P. Rossel, Microelectron. Reliab., vol. 24, No. 2, pp 339-366, 1984).

In a VDMOST shown in FIG. 1A, a field profile in the voltage sustaining layer at V_(B) is shown in FIG. 1B, where a slope of the field versus distance is qN_(D)/E_(s), E_(s) is the permittivity of the semiconductor and q is the electron charge. The change of field through the n-region is qN_(D)/E_(s), 2E_(C)/3. The relation between R_(on) and V_(B) of a n-type voltage sustaining layer is then expressed by R _(on) =W/qμμ _(n) N _(D)=0.83×10⁻⁸ ×V _(B) ^(2.5)Ω.cm²   (3) where μ_(n) is the mobility of the electron and μ_(n)=710×V_(B) ^(0.1)cm/V.sec is used for silicon.

In order to get even lower R_(on) at a given V_(B), some research has been done to optimize the doping profile instead of using a uniform doping, see: [1] C. Hu, IEEE Trans. Electron Devices, vol. ED-2, No. 3, p243 (1979); [2] V. A. K. Temple et al., IEEE Trans. Electron Devices, vol. ED-27, No. 2, p243 (1980); [3] X. B. Chen, C. Hu, IEEE Trans. Electron Devices, vol. ED- 27, No. 6, p985-987 (1982). However, the results show no significant improvement.

BRIEF SUMMARY OF THE INVENTION

The purpose of this invention is to provide a semiconductor high voltage device having a new voltage sustaining layer with better relationship between R_(on) and V_(B). To achieve the above purpose, a semiconductor high voltage devices is provided, which comprises a substrate of a first conductivity type, at least one region of a second conductivity type, and a voltage sustaining layer of the first conductivity type having a plurality of discrete floating (embedded) islands of a second conductivity type between said substrate and said region of the second conductivity type.

According to this invention, an n (or p) type voltage sustaining layer is divided by (n-1) planes into n sub-layers with equal thickness, p (or n) type discrete floating islands are introduced with their geometrical centers on such planes. The average dose N_(T) of the floating islands in each plane is about 2E_(s)E_(c)/3q. For silicon, N _(T)=2E _(s) E _(c)/3q=3.53×10¹² V _(B) ^(0.2)cm⁻²  (4)

With such a floating island, the field is reduced by an amount about 2E_(C)/3 from a maximum value E_(C) at a side of the floating island to a minimum value E_(C)/3 at another side of the floating island so far as the floating island is fully depleted. Each sub-layer is designed to sustain a voltage of V_(B1=V) _(B)/n, and to have a thickness and doping concentration which are almost the same as those form formulas (1) and (2) with V_(B) is replaced by V_(B1), so that when a reverse voltage which is about the breakdown voltage V_(B) is applied over the whole voltage sustaining layer, the maximum field is E_(C) and the minimum field is E_(C)/3, where the locations of the maximum field are not only at the p+-n (or n+-p) junction, but also at the points of each p (or n) island nearest to the n+-n (or p+-p) junction; the locations of the minimum field are not only at the n+-n (or p+-p) junction, but also at the points of each p (or n) islands nearest to the p+-n (or n+-p) junction. An example of the structure of a VDMOST using a voltage sustaining layer of this invention with n=2 is shown in FIG. 3A and the field profile under a reverse voltage of V_(B) is shown in FIG. 3B. Apparently, in such a condition, V_(B)=2WE_(C)/3, where W is the total thickness of the voltage sustaining layer.

It is easy to prove that the above structured voltage sustaining layer including a plurality of floating regions is fully depleted under a reverse bias voltage about V_(B)/2. The flux due to the charges of the ionized donors (or acceptors) under the p (or n) islands are almost totally terminated by the charges of the p (or n) islands. The maximum field is then 2E_(C)/3 and the minimum field is zero, the locations of the maximum field are the same as those under a reverse bias voltage of V_(B).

Apparently, the p (or n) islands make the field not to be accumulated throughout the whole voltage sustaining layer. For a given value of breakdown voltage V_(B), the doping concentration N_(D) can be higher than that in a conventional voltage sustaining layer and the specific on-resistance is much lower than that in a conventional voltage sustaining layer.

Suppose that there are n sub-layers in a voltage sustaining layer. Then, each sub-layer can sustain a voltage of V_(B)/n, where V_(B) is the breakdown voltage of the total voltage sustaining layer. Obviously, instead of (3), the relation of R_(on) and V_(B) of this invention is

$\begin{matrix} \begin{matrix} {R_{on} = {n \times 0.83 \times 10^{- 8}\left( {V_{B}/n} \right)^{2.5}{\Omega.{cm}^{2}}}} \\ {= {0.83 \times 10^{- 8}{V_{B}^{2.5}/n^{1.5}}{\Omega.{cm}^{2}}}} \end{matrix} & (5) \end{matrix}$

Compared to formula (3), it can been seen that the on-resistance of a voltage sustaining layer having n sub-layers is much lower than that of a conventional one.

The inventor has experimented and obtained remarkable results, which show that the on-resistance of a semiconductor device using a voltage sustaining layer with n=2 of this invention is at least lower than ½ of that of a conventional one with the same breakdown voltage, although the real value of R_(on) of a voltage sustaining layer having floating islands is a little higher than the value calculated from expression (5) when n<3, due to the effect that the current path is narrowed by the p-type floating islands. Besides, for minimizing R_(on), the optimum value of N_(T) is slightly different with the expression (4), due to that the negative charges of p-type floating islands are concentrated in the p-regions instead of being uniformly distributed on a plane, whereas these negative charges are used to absorb the flux of ionized donors below that plane.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. In the drawings:

FIG. 1 is the schematic diagram of a prior art VDMOST, where FIG. 1A shows the structure and FIG. 1B shows the field profile.

FIG. 2 shows a voltage sustaining layer structure of this invention, where FIG. 2A shows a voltage sustaining layer structure with islands in one plane. FIGS. 2B and 2C show the structures of the voltage sustaining layer with the floating islands in two planes.

FIG. 3 shows the structure and the field profile of a VDMOST with the voltage sustaining layer of this invention. In FIG. 3A, the voltage sustaining layer of FIG. 2A is used. The field profile of this structure under a reverse voltage of V_(B) is shown in FIG. 3B. In FIG. 3C, a voltage sustaining layer of FIG. 2C is used.

FIG. 4 shows the structure of an IGBT with a voltage sustaining layer of this invention. In FIG. 4A, a voltage sustaining layer of FIG. 2A is used. In FIG. 4B, a voltage sustaining layer of FIG. 2C is used.

FIG. 5 shows a structure of a RMOST with the voltage sustaining layer of this invention shown in FIG. 2A.

FIG. 6 shows a structure of a bipolar junction transistor with the voltage sustaining layer of this invention shown in FIG. 2A.

FIG. 7 shows a structure of a SIT with the voltage sustaining layer of this invention shown in FIG. 2A.

DETAILED DESCRIPTION OF THE INVENTION

All the structures schematically shown in the figures are cross-sectional view. In FIGS. 3-7, the same numeral designates similar parts of a high voltage semiconductor device, where, 1 designates p (or n) island in the voltage sustaining layer; 3 designates n+(or p+) substrate; 4 designates p (or n) source body; 5 designates n+(or p+) source; 6 designates p+(or n+) substrate; 7 designates n (or p) buffer layer; 8 designates p+(or n+) outer base of BJT; 9 designates p+(or n+) grid of SIT; and shaded regions designate oxide regions.

FIG. 2 shows several structures of a voltage sustaining layer according to the invention.

In FIG. 2A, a voltage sustaining layer with p (or n) islands in a plane is shown (i.e., n=2, two sub-layers). In FIG. 2B, a voltage sustaining layer with p (or n) islands disposed in two planes is shown (i.e., n=3, three sub-layers), where each island in the upper plane is vertically arranged over a corresponding island in the lower plane. FIG. 2C shows another voltage sustaining layer with two planes of p (or n) islands (n=3), wherein each of islands in the upper plane is vertically arranged in the middle of two neighboring islands in the lower plane.

The horizontal layout of the voltage sustaining layer can be either interdigitated (finger), or hexagonal (cell), or rectangular (cell). In all the figures of schematic cross-sectional view of the structures, only one or two units (fingers or cells) of the voltage sustaining layer are shown.

The voltage sustaining layer of this invention can be used in many high voltage devices.

1) High Voltage Diode

This can be simply realized by forming two electrodes on the p+-region and the n+-region in any of structures shown in FIG. 2.

2) High Voltage (or Power) VDMOST

FIG. 3A shows a structure of a vertical diffusion metal oxide semiconductor transistor (VDMOS or VDMOST) using the voltage sustaining layer with a plurality of floating islands disposed in one plane, i.e., n=2. FIG. 3B shows the field profile along a line through a center of islands in the voltage sustaining layer and perpendicular to said planes in FIG. 3A. FIG. 3C shows a structure of a VDMOST using a voltage sustaining layer with islands in two planes, i.e., n=3.

The turn-off process of a resultant device is almost as fast as a conventional VDMOST. The turn-on process is like the turn-off process of a conventional IGBT, which consists of a fast stage and a long tail. The long tail is due to the p (or n) islands needing to be charged.

3) High Voltage (or Power) IGBT

FIG. 4A shows a structure of an IGBT using a voltage sustaining layer with n=2. FIG. 4B shows a structure of an IGBT using a voltage sustaining layer with n=3. In order to improve the turn-on process of a VDMOST with the voltage sustaining layer of this invention, only a small amount of minorities is needed to charge the islands in the voltage sustaining layer. This can be done by using a IGBT structure with a very low injection. Investigations by the inventor indicate that an injection ratio of less than 0.1 is enough to make the turn-on process to be almost as fast as the turn-off process and results no long tail. The low injection ratio makes the device operate dominantly by the majority carriers.

4) High Voltage (or Power) RMOST

FIG. 5 shows a structure of an RMOST using a voltage sustaining layer of this invention, where n=2.

5) High Voltage (or Power) BJT

FIG. 6 shows a structure of a bipolar junction transistor using a voltage sustaining layer of this invention, where n=2.

6) High Voltage (or Power) SIT

FIG. 7 shows a structure of a static induction transistor using a voltage sustaining layer of this invention, where n=2.

The design references of a voltage sustaining layer of this invention may be calculated according to above formulas for calculating E_(C) and the average dose of the islands in a plane. For example, at first, a value of a desirable breakdown voltage V_(B) is determined, and the value of E_(C) is calculated from the determined E_(C). Then, from the technology achievable number of sub-layers n, the lateral size of a unit and the width of the islands in a plane, the number of impurity atoms in each island is calculated. The calculated values can be used as the reference values for simulation in CAD if more accurate values are needed.

An example of a process for making a vertical n-IGBT using the voltage sustaining layer of this invention is stated briefly as follows:

-   -   First step: preparing a wafer of a p+-substrate having an         n+-buffer on it;     -   Second step: forming a n-epilayer on said wafer;     -   Third step: growing a thin oxide layer on the epilayer and         forming openings by photo-lithograph;     -   Fourth step: implanting boron through the openings for making         p-islands and then removing the oxide layer;     -   Fifth step: repeat (n-1) times of second step to fourth step.

The following steps are all the same as fabricating a conventional IGBT.

Although the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognized that modifications and variations can be made without departing from the spirit of the invention. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims. 

1. A semiconductor device comprising: a substrate of a first conductivity type; a first region of a second conductivity type, the second conductivity type being opposite the first conductivity type; a voltage sustaining layer of the first conductivity type located between the substrate and the first region; a first substantially uniform embedded region of the second conductivity type located between the substrate and the first region and exclusively in contact with the voltage sustaining layer, the first embedded region being embedded entirely within the voltage sustaining layer and having at least a portion crossing an imaginary plane spaced apart from the substrate and the first region by an approximate equal distance; and a second substantially uniform embedded region of the second conductivity type located between the substrate and the first region and exclusively in contact with the voltage sustaining layer, the second embedded region being embedded entirely within the voltage sustaining layer and having at least a portion crossing the imaginary plane and spaced apart from the first embedded region.
 2. A semiconductor power device comprising: a substrate of a first conductivity type; a first region of a second conductivity type; a voltage sustaining layer of the first conductivity type located between the substrate and the first region, the voltage sustaining layer having a width W defined between the substrate and the first region; a first embedded region of the second conductivity type located entirely within the voltage sustaining layer in alignment between the substrate and the first region, the first embedded region having at least a portion crossing a first imaginary plane parallel to and spaced apart from the substrate by an approximate distance of W/3; and a second embedded region of the second conductivity type having at least a portion crossing a second imaginary plane parallel to and spaced apart from the first region by an approximate distance of W/3.
 3. The semiconductor device according to claim 2 further including a third embedded region of the second conductivity type crossing the first imaginary plane spaced apart from the substrate and also spaced apart from the first and second embedded regions members.
 4. The semiconductor power device according to claim 3 wherein the second embedded region has a geometric center offset from a fourth imaginary plane, the fourth imaginary plane defined through the geometric center of the third embedded region and perpendicular to the second imaginary plane. 